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pcb_finalization #1

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gdorn merged 26 commits from pcb_finalization into main 2024-01-24 23:02:33 +00:00
Conversation 0 Commits 26 Files changed 22 +191215 -12736
22 changed files with 191215 additions and 12736 deletions
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.gitignore vendored Normal file
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*-backups
*/fp-info-cache

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Panels/10_step_seq.scad
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@ -39,7 +39,7 @@ printer_z_fix = 0.2; // this gets added to the base panel's thickness to accoun
label_inset_height = thickness-1;
// Width of module (HP)
width = 17; // [1:1:84]
width = 36; // [1:1:84]
/* [Holes] */
// Four hole threshold (HP)
@ -57,87 +57,104 @@ rail_clearance = 9; // mm from very top/bottom edge and where it is safe to put
// margins from edges
h_margin = hole_dist_side + thickness;
v_margin = hole_dist_top*2;
v_margin = hole_dist_top*2 + thickness;
width_mm = hp_mm(width); // where to put the output jacks
output_column = width_mm - h_margin;
input_column = h_margin;
working_height = height - v_margin*2 - title_font_size;
working_increment = working_height / 7;
// rows up from bottom; these are for steps only
row_1 = v_margin+12;
row_2 = working_increment*1 + row_1;
row_3 = working_increment*2 + row_1;
row_4 = working_increment*3 + row_1;
row_5 = working_increment*4 + row_1;
working_increment = working_height / 6; // generally-useful spacing amount for vertical columns of stuff
col_left = h_margin;
col_middle = col_left + (15.6 + 1.5 + 7 + 8); // pot + led + switch?
col_right = width_mm - h_margin;
// special: the right-hand side tries to squeeze 6 rows into the space of 5
out_working_increment = working_increment * 4 / 5;
out_row_1 = v_margin+12;
out_row_2 = out_working_increment*1 + out_row_1;
out_row_3 = out_working_increment*2 + out_row_1;
out_row_4 = out_working_increment*3 + out_row_1;
out_row_5 = out_working_increment*4 + out_row_1;
out_row_6 = out_working_increment*5 + out_row_1;
out_row_2 = working_increment*1 + out_row_1;
out_row_3 = working_increment*2 + out_row_1;
out_row_4 = working_increment*3 + out_row_1;
out_row_5 = working_increment*4 + out_row_1;
out_row_6 = working_increment*5 + out_row_1;
out_row_7 = working_increment*6 + out_row_1;
//special-case the knob spacing on the right sub-panel
top_row = height - rail_clearance - thickness*2 - 16.5/2; // 16.5 is the diameter of the round part of a pot
rotary_knob_row = top_row - 30;
//special-case the top knobs
top_row = height - v_margin - title_font_size*2;
working_width = width_mm - h_margin;
left_rib_x = thickness * 1;
right_rib_x = width_mm - thickness*2;
// How much horizontal space needed for left-hand and right-hand sub-panels
left_panel_width = 40; // widest element is rotary, at 30mm
right_panel_width = 12; // overkill; currently three 3.5mm jacks needing 8mm
slider_spacing = 12.5; // space between centers of each sliding pot; these are actually 8.8mm but require more on the circuit board for a single through-hole on one side
//calculated x value of exact middle of slider panel (between steps 5 and 6); middle of panel after deducting left/right sub-panels
slider_center = (width_mm - left_panel_width - right_panel_width)/2 + left_panel_width;
slider_bottom = v_margin+12;
// draw panel, subtract holes
union() {
difference(){
color([.1,.1,.1])
panel(width);
// top stuff
// step rotary switch? Special: this needs measuring, and leaving space for a label
translate([col_left+h_margin, top_row, 0]) pot_p160();
// internal clock rate
translate([col_right-h_margin, top_row, 0]) pot_p160();
translate([col_left, row_5, 0]) make_step();
translate([col_left, row_4, 0]) make_step();
translate([col_left, row_3, 0]) make_step();
translate([col_left, row_2, 0]) make_step();
translate([col_left, row_1, 0]) make_step();
translate([col_middle, row_5, 0]) make_step();
translate([col_middle, row_4, 0]) make_step();
translate([col_middle, row_3, 0]) make_step();
translate([col_middle, row_2, 0]) make_step();
translate([col_middle, row_1, 0]) make_step();
// Top left: clock in, speed
// clock in
translate([col_right, out_row_6, 0]) audio_jack_3_5mm();
translate([col_left, top_row, 0]) audio_jack_3_5mm();
//clock rate
translate([col_left+20, top_row, 0])
rotate([0, 0, 180])
pot_p160();
// Left side: meta-step controls
// step rotary switch - this needs a _big_ knob, these are not easy to actuate, plus space for well-aligned, well-printed numbers
translate([col_left+15, rotary_knob_row, 0]) rotary_switch();
// step (manual) -- this is actually a pushbutton momentary, but roughly same dimensions as toggle switch
translate([col_left+5, out_row_3, 0]) toggle_switch_6mm();
// reset (manual) -- this is actually a pushbutton momentary, but roughly same dimensions as toggle switch
translate([col_left+20, out_row_3, 0]) toggle_switch_6mm();
// run/stop (switch)
translate([col_left+5, out_row_2, 0]) toggle_switch_6mm();
// once/continuous (switch)
translate([col_left+20, out_row_2, 0]) toggle_switch_6mm();
// cv range (switch between 2.5v and 5v max)
translate([col_left+15, out_row_1, 0]) toggle_switch_6mm();
// clock out
translate([col_right, out_row_5, 0]) audio_jack_3_5mm();
// reset
translate([col_right, out_row_4, 0]) audio_jack_3_5mm();
// gate out
translate([col_right, out_row_3, 0]) audio_jack_3_5mm();
// cv out
// gate out
translate([col_right, out_row_2, 0]) audio_jack_3_5mm();
// cv switch
// cv out
translate([col_right, out_row_1, 0]) audio_jack_3_5mm();
// steps: slider, led, switch
// Note: don't mess with the multipliers here, tweak the variables themselves
translate([slider_center-slider_spacing*.5, slider_bottom, 0]) make_step();
translate([slider_center-slider_spacing*1.5, slider_bottom, 0]) make_step();
translate([slider_center-slider_spacing*2.5, slider_bottom, 0]) make_step();
translate([slider_center-slider_spacing*3.5, slider_bottom, 0]) make_step();
translate([slider_center-slider_spacing*4.5, slider_bottom, 0]) make_step();
translate([slider_center+slider_spacing*.5, slider_bottom, 0]) make_step();
translate([slider_center+slider_spacing*1.5, slider_bottom, 0]) make_step();
translate([slider_center+slider_spacing*2.5, slider_bottom, 0]) make_step();
translate([slider_center+slider_spacing*3.5, slider_bottom, 0]) make_step();
translate([slider_center+slider_spacing*4.5, slider_bottom, 0]) make_step();
}
// label the whole thing?
// translate([width_mm/2, height-hole_dist_top-10, 0]) label("Fireball VCO", size=10);
// ribs
// ribs - reinforcements and barriers against shorts on the rails
translate([left_rib_x, rail_clearance, 0])
v_wall(h=4, l=height-rail_clearance*2-thickness);
translate([right_rib_x, rail_clearance, 0])
@ -146,30 +163,10 @@ union() {
// top horizontal rib
translate([left_rib_x, height-rail_clearance-thickness, 0])
h_wall(h=4, l=right_rib_x);
// middle horizontal rib
translate([left_rib_x, top_row-rail_clearance-thickness, 0])
h_wall(h=1.6, l=right_rib_x);
// middle-bottom h rib
translate([left_rib_x, rail_clearance+15+thickness, 0])
h_wall(h=1.6, l=right_rib_x);
// bottom horizontal rib
translate([left_rib_x, rail_clearance, 0])
h_wall(h=4, l=right_rib_x);
// one more vertical to mount the circuit board to, dead center
translate([width_mm/2-thickness/2, rail_clearance+15+thickness, 0])
v_wall(h=4, l=top_row-rail_clearance*2-thickness-15);
// PCB holder
translate([width_mm/2-thickness/2+1.15/2, rail_clearance+15+thickness, 0])
pcb_holder(h=10, l=top_row-rail_clearance*2-15-thickness, th=1.15, wall_thickness=1);
// lower h-rib reinforcer
}
module make_surface(filename, h) {
@ -234,23 +231,46 @@ module nys325_midi_socket() {
cylinder(r=1.6, h=thickness*2+1);
}
module audio_jack_3_5mm() {
module audio_jack_3_5mm(vertical=true) {
translate([0, 0, -1]) cylinder(r=3, h=thickness*2+1);
if (vertical) {
translate([-9/2, -10.5/2, 0]) cube([9, 10.5, .0001]);
} else {
translate([-10.5/2, -9/2, 0]) cube([10.5, 9, .0001]);
}
}
module toggle_switch_6mm() {
translate([0, 0, -1]) cylinder(r=3, h=thickness*2+1);
translate([-8/2, -13/2, 0]) cube([8, 13, .0001]);
}
module toggle_switch_6_8mm() {
translate([0, 0, -1]) cylinder(r=3.4, h=thickness*2+1);
}
// http://www.mouser.com/ds/2/414/Datasheet_RotaryPanelPot_P160series-1133272.pdf
module rotary_switch(){
translate([0, 0, -1]) cylinder(r=5, h=thickness*2);
//hole for anchor
translate([17.36/2 + 3/2, 0, -1]) cylinder(r=1.5, h=thickness);
// visual indicator of space switch takes up
translate([0, 0, 0]) cylinder(r=14, h=.0001);
}
//
module pot_p160(anchor_hole="left") {
translate([0, 0, -1]) cylinder(r=3.75, h=thickness*2);
// hole for anchor; with translate() ends up being h-1 deep
if (anchor_hole=="left" || anchor_hole=="both") {
translate([7.8, 0, -1]) cylinder(r=1.5, h=thickness);
translate([0, 13/2, 0]) cube([17, 13, .0001], center=true);
}
if (anchor_hole=="right" || anchor_hole=="both") {
translate([-7.8, 0, -1]) cylinder(r=1.5, h=thickness);
translate([0, 0, 0]) cube([17, 13, .0001], center=true);
}
// visual indicator of space pot body takes up
translate([0, 0, 0]) cylinder(r=16.5/2, h=.0001);
}
module pot_wh148() {
@ -259,16 +279,31 @@ module pot_wh148() {
translate([7.8, 0, -1]) cylinder(r=1.3, h=thickness);
}
module pot_0547() {
// slider pot slit
translate([-1.25, 0, -1]) cube([2.5, 52, thickness*2]);
// visual indicator
translate([-8.8/2, -4, 0]) cube([8.8, 60.25, .0001]);
}
module led_5mm() {
// make a hole for a 5mm led, with a hair of margin
translate([0, 0, -1]) cylinder(r=2.575, h=thickness*2+2);
}
module make_step() {
module make_step(bottom_element="switch") {
// generate holes for a pot, an LED, and a switch
pot_p160();
translate([8, 0, 0]) led_5mm();
translate([8+7, 0, 0]) toggle_switch_6_8mm();
if (bottom_element=="pot"){
pot_0547();
translate([0, 55+8, 0]) led_5mm();
translate([0, 55+24, 0]) toggle_switch_6mm();
} else if (bottom_element=="switch") {
toggle_switch_6mm();
translate([0, 16, 0]) pot_0547();
translate([0, 55+24, 0]) led_5mm();
}
}

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README.md
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@ -1,40 +1,63 @@
Notes:
Features already done:
- Could make the clock oscillilator an external module, with the SEQ listening for a clock on the 16-pin IDC connector when nothing is plugged into CLOCK.
- A notable issue with this design is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v or even much less.
This can be fixed by increasing the gain on the CLOCK op-amp from 1 to something more decisive, like 3x. Then a signal as low as 2v could works as an external clock.
- One idea: add a switch to disable the clock, and a momentary-on button to advance the step manually. This requires hardware de-bouncing to avoid multiple triggers on each
button push.
- Another idea: trigger (button push or CV) starts the sequence, which plays through exactly once, and then stops? Possibly put a switch between pin 15 and the three-way junction, and a NO switch across that switch… it might be fine, just go between +12v and pin 15 with the NO. with the bonus that you can push it to reset a continually-running pattern whenever you want
- Could replace step IDs with a 7-segment display with a diode matrix to select segments from each step.
- Could add a global/master pitch control/modulation function with a knob and with CV in implement a DC offset via non-inverting op-amp.
- A CV in that pauses the clock and keeps current gate open whenever the voltage exceeds a certain threshold (perhaps useful for feedback effects where one sequencer is interacting with another). More of an experimental functionality
- Input/Output CV to permit chaining of Unseen Servants. For example, Unseen Servant 1 plays its sequence, then hands off to Unseen Servant 2, which plays its sequence and then hands back to Unseen Servant 1 (or hands of to Unseen servant 3, etc.). A jacked CV out with no return implies a play sequence once function?
- Internal clock with manual control.
- Clock in socket with amplifier to handle weaker (<6v) signals
- Clock out socket, with option to send to 16-pin cable when nothing is plugged into it.
- Manual one-step-forward via momentary push button.
- CV out, with switch for two different ranges (e.g. 0-2.5v / 0-5v)
- Gate out, with probably +12v gates.
- Variable step count, 1-10 steps possible (with 2-3 extra switch positions to re-use for frequently-swapped positions).
- External reset via socket.
- External reset via momentary push button.
- Play continuously or play once (switch to select mode, then use manual reset button to run once)
- Pause sequence and resume - a function of the run/stop switch. Will hold open the gate of the last step and output CV continously while paused.
- Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first.
More feature ideas:
- Trigger out - could be done with a capacitor / resistor pair, see Fireball's hard sync input.
- But could also be done at the module that requires a trigger-sized pulse on input.
- Portamento (aka slew rate controller aka glide).
- Knob version fairly simple.
- CV version maybe possible, but a much bigger circuit. Haven't found a simple implementation. Can be done externally with a more complex module, several variations on the classic "Maths" module exist for modifying a CV in complex ways.
- CV in to pause the sequence.
Probably can't do, or impractical:
- CV-controlled clock. Presumably the CV in controls the clock rate? Possible in the digital realm, or perhaps an external CV-to-pulse-rate module? Is this even useful?
- Seven-segment display. Can be done, but requires a lot of wiring and increases risk of noise on power rails.
Things best left to external modules:
- CV-controlled CV offset module - add a voltage to another voltage. Useful here for pitching up from a base.
UI:
11 potentiometers
11 SPDT switches
1 rotary switch, 5+ positions
10 LEDs
3 sockets
- 11 potentiometers
- 13 SPDT switches (many used as SPST)
- 2 momentary pushbutton switches
- 1 rotary switch, 5+ positions
- 10 LEDs
- 6 sockets
Potentiometers:
One potentiometer per step, to set output voltages. (10)
One potentiometer for internal clock rate.
- One potentiometer per step, to set output voltages. (10)
- One potentiometer for internal clock rate.
Switches:
One SPDT switch per step, to enable/disable gate per step. (10)
One multi-pole rotary switch to set number of steps. Exact configuration TBD.
One SPDT switch to adjust CV output range, switch between 5v and 2.5v max.
- One SPST switch per step, to enable/disable gate per step. (10)
- One multi-pole rotary switch to set number of steps. Exact configuration TBD.
- One SPDT switch to adjust CV output range, switch between 5v and 2.5v max (or whatever is configured).
- Momentary-normal-off pushbutton to manually step.
- SPST switch to disable clock (pause).
- SPST switch to disable reset (run once).
- Momentary-normal-off pushbutton to manually reset.
LEDs:
One per step, to indicate current step. (10)
- One per step, to indicate current step. (10)
Sockets:
CLOCK in
CLOCK out
RESET in
GATE out
CV out
- CLOCK in
- CLOCK out
- RESET / CASCADE in
- RESET / CASCADE out
- GATE out
- CV out

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Schematics/Kassutronics_Slope_Build_Docs_2.0A.pdf Normal file
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Schematics/Unseen Servant/Unseen Servant.kicad_dru Normal file
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@ -0,0 +1,102 @@
(version 1)
#Kicad 7
# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
(constraint track_width (min 5mil))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (outer layer)"
(constraint clearance (min 5mil))
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type"))
# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 3.5mil))
(layer inner)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (inner layer)"
(constraint clearance (min 3.5mil))
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type"))
# silkscreen (Kicad 7 only)
(rule "Minimum Text"
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
(layer "?.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint silk_clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
# edge clearance
(rule "Trace to Outline"
(constraint edge_clearance (min 0.2mm))
(condition "A.Type == 'track'"))
# This would override board outline and milled areas
#(rule "Trace to V-Cut"
# (constraint clearance (min 0.4mm))
# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
# drill/hole size
(rule "drill hole size (mechanical)"
(constraint hole_size (min 0.2mm) (max 6.3mm)))
(rule "Minimum Via Hole Size"
(constraint hole_size (min 0.2mm))
(condition "A.Type == 'via'"))
(rule "Minimum Via Diameter"
(constraint via_diameter (min 0.45mm))
(condition "A.Type == 'via'"))
(rule "PTH Hole Size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated()"))
(rule "Minimum Non-plated Hole Size"
(constraint hole_size (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
(rule "Minimum Castellated Hole Size"
(constraint hole_size (min 0.6mm))
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
# clearance
(rule "hole to hole clearance (different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Net != B.Net"))
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "NPTH to Track clearance)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "PTH to Track clearance)"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && B.Type == 'track'"))
(rule "Pad to Track clearance)"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && B.Type == 'track'"))

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Schematics/Unseen Servant/Unseen Servant.kicad_pcb
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Schematics/Unseen Servant/Unseen Servant.kicad_prl
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@ -1,12 +1,14 @@
{
"board": {
"active_layer": 31,
"active_layer_preset": "All Layers",
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,

123
Schematics/Unseen Servant/Unseen Servant.kicad_pro
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@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -33,9 +34,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.5,
"height": 0.85,
"width": 0.85
"drill": 1.0,
"height": 1.7,
"width": 1.7
},
"silk_line_width": 0.15,
"silk_text_italic": false,
@ -62,20 +63,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -85,9 +92,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -96,7 +108,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -104,20 +115,65 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.25,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.25,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": true,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
@ -130,7 +186,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -314,18 +371,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -335,6 +397,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -352,7 +415,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -363,16 +426,48 @@
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"track_width": 0.3,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6,
"via_diameter": 1.0,
"via_drill": 0.5,
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Power",
"pattern": "+12V"
},
{
"netclass": "Power",
"pattern": "-12V"
},
{
"netclass": "Power",
"pattern": "GND"
}
]
},
"pcbnew": {
"last_paths": {
@ -388,6 +483,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
@ -419,7 +516,11 @@
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},

8481
Schematics/Unseen Servant/Unseen Servant.kicad_sch
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102
Schematics/Unseen Servant/Unseen Servant_counter_board_noncanonical.kicad_dru Normal file
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@ -0,0 +1,102 @@
(version 1)
#Kicad 7
# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
(constraint track_width (min 5mil))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (outer layer)"
(constraint clearance (min 5mil))
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type"))
# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 3.5mil))
(layer inner)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (inner layer)"
(constraint clearance (min 3.5mil))
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type"))
# silkscreen (Kicad 7 only)
(rule "Minimum Text"
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
(layer "?.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint silk_clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
# edge clearance
(rule "Trace to Outline"
(constraint edge_clearance (min 0.2mm))
(condition "A.Type == 'track'"))
# This would override board outline and milled areas
#(rule "Trace to V-Cut"
# (constraint clearance (min 0.4mm))
# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
# drill/hole size
(rule "drill hole size (mechanical)"
(constraint hole_size (min 0.2mm) (max 6.3mm)))
(rule "Minimum Via Hole Size"
(constraint hole_size (min 0.2mm))
(condition "A.Type == 'via'"))
(rule "Minimum Via Diameter"
(constraint via_diameter (min 0.45mm))
(condition "A.Type == 'via'"))
(rule "PTH Hole Size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated()"))
(rule "Minimum Non-plated Hole Size"
(constraint hole_size (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
(rule "Minimum Castellated Hole Size"
(constraint hole_size (min 0.6mm))
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
# clearance
(rule "hole to hole clearance (different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Net != B.Net"))
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "NPTH to Track clearance)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "PTH to Track clearance)"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && B.Type == 'track'"))
(rule "Pad to Track clearance)"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && B.Type == 'track'"))

39556
Schematics/Unseen Servant/Unseen Servant_counter_board_noncanonical.kicad_pcb Normal file
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77
Schematics/Unseen Servant/Unseen Servant_counter_board_noncanonical.kicad_prl Normal file
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@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "Unseen Servant_counter_board_noncanonical.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

534
Schematics/Unseen Servant/Unseen Servant_counter_board_noncanonical.kicad_pro Normal file
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@ -0,0 +1,534 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.0,
"height": 1.7,
"width": 1.7
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.25,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.25,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": true,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
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1,
0,
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0,
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2,
2,
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],
[
0,
0,
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0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
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0,
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],
[
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0,
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0,
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],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
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],
[
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[
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[
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2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "Unseen Servant.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6,
"via_diameter": 1.0,
"via_drill": 0.5,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Power",
"pattern": "+12V"
},
{
"netclass": "Power",
"pattern": "-12V"
},
{
"netclass": "Power",
"pattern": "GND"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"0183ccee-e064-4ef2-a2e7-6b862e9a0382",
""
]
],
"text_variables": {}
}

102
Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_dru Normal file
View file

@ -0,0 +1,102 @@
(version 1)
#Kicad 7
# 2-layer, 1oz copper
(rule "Minimum Trace Width (outer layer)"
(constraint track_width (min 5mil))
(layer outer)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (outer layer)"
(constraint clearance (min 5mil))
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type"))
# 4-layer
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 3.5mil))
(layer inner)
(condition "A.Type == 'track'"))
(rule "Minimum Trace Spacing (inner layer)"
(constraint clearance (min 3.5mil))
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type"))
# silkscreen (Kicad 7 only)
(rule "Minimum Text"
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
(layer "?.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint silk_clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
# edge clearance
(rule "Trace to Outline"
(constraint edge_clearance (min 0.2mm))
(condition "A.Type == 'track'"))
# This would override board outline and milled areas
#(rule "Trace to V-Cut"
# (constraint clearance (min 0.4mm))
# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
# drill/hole size
(rule "drill hole size (mechanical)"
(constraint hole_size (min 0.2mm) (max 6.3mm)))
(rule "Minimum Via Hole Size"
(constraint hole_size (min 0.2mm))
(condition "A.Type == 'via'"))
(rule "Minimum Via Diameter"
(constraint via_diameter (min 0.45mm))
(condition "A.Type == 'via'"))
(rule "PTH Hole Size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated()"))
(rule "Minimum Non-plated Hole Size"
(constraint hole_size (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
(rule "Minimum Castellated Hole Size"
(constraint hole_size (min 0.6mm))
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
# clearance
(rule "hole to hole clearance (different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Net != B.Net"))
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "NPTH to Track clearance)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "PTH to Track clearance)"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && B.Type == 'track'"))
(rule "Pad to Track clearance)"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && B.Type == 'track'"))

47783
Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_pcb Normal file
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77
Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_prl Normal file
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{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
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],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "Unseen Servant_slider_board_noncanonical.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

534
Schematics/Unseen Servant/Unseen Servant_slider_board_noncanonical.kicad_pro Normal file
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.0,
"height": 1.7,
"width": 1.7
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.25,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.25,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": true,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
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"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
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"pinned_symbol_libs": []
},
"meta": {
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"version": 1
},
"net_settings": {
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"clearance": 0.2,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
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"wire_width": 6
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{
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"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6,
"via_diameter": 1.0,
"via_drill": 0.5,
"wire_width": 6
}
],
"meta": {
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},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
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"netclass": "Power",
"pattern": "+12V"
},
{
"netclass": "Power",
"pattern": "-12V"
},
{
"netclass": "Power",
"pattern": "GND"
}
]
},
"pcbnew": {
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"idf": "",
"netlist": "",
"specctra_dsn": "",
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"schematic": {
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"drawing": {
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}

1
Schematics/Unseen Servant/fp-info-cache
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Schematics/circuit.pdf Normal file
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