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Back-9.127902e-01 0.000000e+00 vertex -9.090385e+01 9.578066e+01 2.655000e+01 facet normal -0.286343 -0.11861 0.950757 facet normal -0.0728683 -0.0676734 -0.995043 vertex -6.37314 -7.70061 0.0405804 facet normal -0.135125 0.297024 0.945261 facet normal -0.195099 0.980784 -2.05895e-07 facet normal 3.318485e-001 -5.689129e-001 7.524723e-001 facet normal 0.0623609 -0.633162 0.771503 vertex 1.6703 -8.39715 5.56266 facet normal -0.462425 -0.865137 0.194169 vertex 3.89968 9.41467 2.19603 vertex 9.8813 2.36142 0 facet normal -6.869846e-01 -7.266719e-01 3.388247e-04 facet normal -0.195098 -0.980784 -7.21329e-06 vertex 0.4 3.26571 11.5393 vertex 1.45059 3.07081 15.6068 vertex 0.4 -3.00952 6.59 vertex 2.42184 2.42184 18.1498 facet normal -4.395889e-001 7.536203e-001 4.886902e-001 vertex 2.779774e+000 -3.140328e+000 2.484855e+001 facet normal 0.282966 -0.360203 0.888923 facet normal -0.615997 -0.526063 0.586349 vertex 6.27392 1.68379 19.9697 facet normal -0.115344 0.000261241 0.993326 vertex -6.43809 0.596366 7.83604 facet normal 0.000275588 0.115008 0.993365 vertex -6.33525 0.41258 7.82405 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt A couple more minor clearance tweaks Subject: [PATCH 2/2] Update README.md 3e868f13c4dc33c20ca33a0cc8f51c9d63e1c081 updated C14 footprint, traces, groundplane master PSU/Synth Mages Power Word Stun.kicad_pcb Normal file View File Synth_Manuals/minimoog_operation_manual_1.pdf Executable file View File From 7e24b3de83ed5d44b4cd8ae11f345f795b25c6b7 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs Footprint.
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