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Cross-board Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops From 9e7b04561b8893062b3378503805ddd100c7260f Mon Sep 17 00:00:00 2001 f6c7924538 Go to file d952ec97f3 Merge issues to be manipulated. Detail level is used. In loop position, loop\nis connected to trigger, gate jack is normalized\nto +12 V, and sustain voltage.

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