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Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-F_Paste.gbr Normal file Unescape Schematics/SynthMages.pretty/Perfboard_2x12.kicad_mod Normal file Unescape Fireball/Fireball_panel.kicad_pcb Normal file View File Panels/futura light bt.ttf differ From 9060b76361734f9abf9a1c676dd9110e9ced917b Mon.

-3.978371e-01 facet normal 5.7231e-05.
1.32079 1.35458 vertex 9.38269 1.41421 6.17306.

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