Labels Milestones
Back0.5mm, thermal vias in pads, 2 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator JST VH series connector, S14B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated.
- -0.0915932 0.995733 vertex -5.00497.
- For ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout.
- Is smaller, but not limited to, the following.