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A.Type")) # 4-layer condition "A.Type == 'track' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == A.Type && A.Net == B.Net" (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == A.Type" condition "A.Type == 'via'" condition "A.Type == 'track'" condition "A.Type == 'via'" (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net" condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'track' && B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'track'" condition "A.Type == 'via' && B.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH 10/18] More tweaks after pro review Fireball/Fireball.kicad_pro | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace Added schmancy pcb for v1 build Schematics/bad_trace_v1.jpeg Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-F_Cu.gbr Normal file Unescape Hardware/Panel/precadsr-panel/sym-lib-table Normal file Unescape Hardware/PCB/precadsr/ao_symbols.lib Normal file Unescape From 9f9f6acf76f746b4755da71c07bb656091774052 Mon Sep 17 00:00:00 2001 Latest commits for file Panels/Futura Heavy BT.ttf From 51a08380a94a002bd27260320b805b082bdb3963 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Gerbers .../precadsr_aux_Gerbers/precadsr-B_Cu.gbr | 518 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr | 266 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 15 .../precadsr_panel_al-F_Mask.gbr | 47 .../precadsr_panel_al-F_Paste.gbr | 15 .../precadsr-panel-PasteTop.gtp | 15 .../PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr | 128.

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