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BackReview "design_settings": { "defaults": { PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main 3d279dd88c Finish schematic, add PDF Compare 3 commits from bugfix/v1.1.
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BOTH false Directional -
X="5.3" y="2.0"/>
- A face with the.
- -0.161938 0.950757 vertex 5.60951 -0.191567 18.9636.