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BackFolders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Latest commits for file Images/retrigger.png Latest commits for file Dual_VCA.diy Add VCA shaek layout Add VCA shaek layout Adding SynthMages footprint library create mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Paste.gbr create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_Paste.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-16_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/MAGIC MOUTH.png Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SOT-23_Handsoldering.kicad_mod Normal file View File 3D Printing/Pot_Knobs/Pot3.STL Executable file View File Images/loop.png Normal file View File Synth Mages Power Word Stun.kicad_prl main VCA/README.md 9 lines main synth_tools/Schematics/SynthMages.pretty/POT_2_PIN_Header.kicad_mod 44 lines 1705ad98fb Put title box in PDF export' (#4) from schematic into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring D36/R47 too close Testing before powering up: Clock In - U1-13 (can get at from top when assembled - Stop Switch - 10 - center_adjust; center_col = width_mm/2.
- BT font files These were used.
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X="5.4" y="2.4"/>
4.308032e-01 9.024458e-01 -3.431192e-04 vertex -9.446753e+01 9.232659e+01 2.550000e+00.