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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= 744b72ef7e0d94fccfae99ec3cb3514981ac4616 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version b22080a808 More experimentation with panel alignment before printing Messing around with panel title fonts More experimentation with panel alignment before printing 9a2ab6dc7f initial notes for v1 front panel 82024e96c9 updated C14 footprint, traces, groundplane updated C5 footprint & tracing; schematic annotation 2cbdb94ba94f485ce4abcb1f14e2e5f15d016647 updates the potentiometer pads and thermal vias; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.5mm; see section 6.6 of http://www.st.com/resource/en/datasheet/DM00273119.pdf X1-WLB0909, 0.89x0.89mm, 4 Ball, 2x2 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h747xi.pdf DFN, 6 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/MAX4460-MAX4462.pdf#page=19, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tdfn-ep/21-0137.pdf), generated with kicad-footprint-generator JST VH series connector, SM10B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated.
- Normal -0.0816197 -0.758952 0.646011 facet normal 0.995184 -0.0980262.
- 1k to U2-8 (AND NOT short to U2-10.
- Vertex -5.40904 -4.29047 7.37319 vertex 5.40021 -4.41978.
- Dot12 Dot13 W1 L2 .