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BackIgnored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/3PDT-toggle-switch-1M-seriesx.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SOT-23_Handsoldering.kicad_mod Normal file View File Panels/FireballSpell.png Executable file View File Schematics/shaek_try_1.diy Normal file View File 3D Printing/Cases/Eurorack Modular Case/DSC03778.JPG Executable file View File 3D Printing/Pot_Knobs/potentiometre_v3.stl create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-8_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9
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- Normal 0.0995007 8.52891e-07 -0.995037 vertex 4.25579 -9.04402 0.0469873.
- 4.085376e+000 1.627355e+000 2.484855e+001 facet normal.