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BackDrill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Minor layout tweaks merged pull request 'Put title box in PDF export Schematics/Fireball_VCO.pdf | Bin 11930 -> 0 bytes Latest commits for file Fireball/Fireball.kicad_pcb tweaks layout with input from sam 32 "B.Adhes" user "B.Adhesive" (33 "F.Adhes" user "F.Adhesive" (34 "B.Paste" user (35 "F.Paste" user (36 B.SilkS user (37 F.SilkS user hide (0 "F.Cu" signal (31 B.Cu signal (32 B.Adhes user (33 F.Adhes user (34 B.Paste user (35 F.Paste user hide (48 B.Fab user (49.
- 107 (end 156 74.5 (end.
- 44.00x30.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf Laird Technologies.
- 0.115649 0.00128232 0.993289 vertex 7.11568 1.05741 7.9151 facet.
- Block, 1732535 (https://www.phoenixcontact.com/online/portal/gb/?uri=pxc-oc-itemdetail:pid=1732535), generated.
- Normal 0.081922 0.0818425 0.993273 vertex 5.22724 5.17002 6.86195.