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| 1656 create mode 100644 Panels/title_test_18.stl create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/MIRROR IMAGE.png differ Binary files /dev/null and b/Panels/FireballSpell_Large_bw.xcf differ From 52b504dd7cabbf7261c98563d42b1772d3bf6825 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete '3D Printing/Panels/image.png' 935360b933 Delete '3D Printing/Panels/FIREBALL VCO.png' da12ac6a39 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/MAGIC MISSILE VCF.png' **UI:** -2 5mm LEDs -Consider: 1 simple on/off switch/button/knob/etc. - 2 pin Molex header Operational amplifier, DIP-8 From 1705ad98fb4243c88ad227e3cad9c42bb94c7269 Mon Sep 17 00:00:00 2001 Subject: [PATCH] edits README.md file adds README.md file 2537badf28 updates led holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes to 5mm + unplated, and revises jack footprint b284a71188 gets comfier with gitignore and git rm --cache 19116ba39d Apply jlcpcb's design rules, small fixes for those Fireball/Fireball.kicad_pro | 93 Fireball/Fireball.kicad_sch | 64 Fireball/fp-info-cache | 86150 master ttrss-plugin- _comics/init.php 366 lines From d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 Mon Sep 17 00:00:00 2001 Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.lck # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks From c6e6a61475df01d4832847208a59070c5a40c498 Mon Sep 17 00:00:00 2001 Subject: [PATCH] light tweaks light tweaks light tweaks checkpoint after roughing out middle PCB checkpoint after roughing out middle PCB checkpoint after roughing out middle PCB .../Unseen Servant/Unseen Servant.kicad_sch | 647 Latest commits for branch v1.1 Finish PCBs Finish PCBs .../Unseen Servant/Unseen Servant.kicad_pcb | 2 | 1N5817 | Schottky diode | | J1 | 1 | 10nF | Ceramic capacitor | | Tayda | A-004 | | | Tayda | A-159 | .

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