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B.Cu" "Notes": "Layer F.SilkS" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Paste" "Notes": "Layer F.Paste" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: merged pull request 'Put title box in PDF export' (#4) from schematic.

Hardware/PCB/precadsr/precadsr.kicad_pcb Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch Normal.
-0.0865364 0.878606 0.469642 facet normal.
-4.6286 21.7443 facet normal 0.0808324.
Jack, plus space between them.

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