Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks Finish schematic, add PDF Features already done: Internal clock with manual control. Clock in socket with amplifier to handle weaker (<6v) signals Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. - Trigger out - GATE out - Gate out (could normal to Reset In Pause CV In - diode to U2-3 - Clock rate goes down when resistance goes up, opposite to expectation. Glide fix