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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File 3D Printing/Cases/Eurorack 2-Row/rail.scad Executable file Unescape Schematics/circuit.pdf Normal file View File Find and replace last few thin traces, fix teardrops and gnd fill Corrected: Shifted C5 so one of the Pelorinho