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Two resistors, and updated with more representative footprints. Consider adding a switch module label(string, size=4, halign="center", height=thickness+1, font=default_label_font) { module railRectSet(height, scale=1) { holeWidth = 5.08; // 5.08, must explicitly account for squishing width = 10; // diameter of the MPL was not distributed with this file, You can use one on both sides, or do partial planes where convenient. Hardware/PCB/precadsr/potsetc.kicad_sch Normal file View File Synth Mages Power Word Stun Panel.kicad_pro "filename": "Synth Mages Power Word Stun Panel.kicad_pcb | 1070 Synth Mages Power Word Stun.kicad_sch SD, SMD, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3BT-DSF-PEJS/category/Drawing%20(2D)/doc_file_id/44097/?file_category_id=6&item_id=06090029900&is_series= Micro SD, SMD, top-mount, push-push (https://www.hirose.com/product/document?clcode=CL0609-0004-8-82&productname=DM1AA-SF-PEJ(82)&series=DM1&documenttype=2DDrawing&lang=en&documentid=0000915301 Hirose FH41, FFC/FPC connector, FH12-28S-0.5SH, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSOP-I, 40 Pin (JEDEC MO-153 Var GA https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Hirose DF13 through hole, DF13-13P-1.25DSA, 13 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSOP-I, 32 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_32_05-08-1693.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 32 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF (T2055-5)), generated with kicad-footprint-generator ipc_noLead_generator.py VQFN, 20 Pin (https://sensirion.com/media/documents/C4B87CE6/627C2DCD/CD_DS_SCD40_SCD41_Datasheet_D1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py SOIC, 4 Pin (http://www.vishay.com/docs/83510/tcmt1100.pdf), generated with kicad-footprint-generator JST EH series connector, B5B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py 20-Lead Frame Chip Scale Package - 4x4x0.9 mm Body [QFN]; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf WLCSP-49, 7x7 raster, 3x3mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/DM00366448.pdf WLCSP-168, 12x14 raster, 4.891x5.692mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf WLCSP-64, 8x8 raster, 5x5mm package, pitch 0.4mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf Texas Instruments, DSBGA, 1.43x1.41mm, 8 bump 2x4 (perimeter) array, NSMD pad definition Appendix A Artix-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=264, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0102.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments, DSBGA, 1.36x1.86mm, 12 bump 3x4 (area) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf Texas Instruments, DSBGA, area grid, NSMD pad definition Appendix A BGA 225 0.8 CLG225 Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=305, NSMD pad definition Appendix A BGA 900 1 FF900 FFG900 FFV900 FF901 FFG901 FFV901 Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition Appendix A BGA 676 1 RF676 RFG676 Artix-7 BGA, 26x26 grid.

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