Labels Milestones
BackStrip, HLE-140-02-xxx-DV-BE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator JST SH series connector, 53780-1270 (), generated with kicad-footprint-generator connector Molex PicoBlade series connector, 504050-0691 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP44: plastic thin shrink small outline transistor (see http://www.onsemi.com/pub/Collateral/NST3906F3-D.PDF 3-pin SuperSOT package https://www.fairchildsemi.com/package-drawings/MA/MA03B.pdf 6-pin SuperSOT package http://www.mouser.com/ds/2/149/FMB5551-889214.pdf 8-pin SuperSOT package, http://www.icbank.com/icbank_data/semi_package/ssot8_dim.pdf Power MOSFET package, 3x3mm (see https://www.fairchildsemi.com/datasheets/FD/FDMC8032L.pdf Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm VSSOP DCU R-PDSO-G8 Pitch0.5mm VSSOP-8 3.0 x 3.0 VSSOP, 10 Pin (https://www.ti.com/lit/ml/mpqf186d/mpqf186d.pdf Texas RSE0010 UQFN NoLead Texas VQFN-HR, 11 Pin, https://www.ti.com/lit/ml/mpqf579/mpqf579.pdf Texas WQFN, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_10_10.pdf), generated with kicad-footprint-generator Molex KK 396 Interconnect System, old/engineering part number: 22-27-2131, 13 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 52 Pin (JEDEC MO-153 Var BC-1 https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator ipc_gullwing_generator.py MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator Mounting Hardware, inside blind hole M1.6, height 4, Wuerth electronics 9774055951 (https://katalog.we-online.de/em/datasheet/9774055951.pdf), generated with kicad-footprint-generator Molex Nano-Fit Power Connectors, old mpn/engineering number: 5566-14A, example for new mpn: 39-29-4049, 2 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator connector wire 2sqmm strain-relief Soldered wire connection with feed through strain relief, for a single 1.5 mm² wires, basic insulation, conductor diameter 1.4mm, outer diameter 4.4mm, size source Multi-Contact FLEXI-E 1.0 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times 1 mm² wire, reinforced insulation, conductor diameter 1.25mm, outer diameter 3.9mm, size source Multi-Contact FLEXI-E 0.1 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator ipc_noLead_generator.py 14-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_32_05-08-1734.pdf DFN44 8.9x5, 0.4P; CASE 506BU-01 (see ON Semiconductor 506CN.PDF DC8 Package 8-Lead Plastic SO, Exposed Die Pad (TI DDA0008B, see http://www.ti.com/lit/ds/symlink/lm3404.pdf 8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf Texas Instruments EUW 7 Pin (https://b2b-api.panasonic.eu/file_stream/pids/fileversion/2787), generated with kicad-footprint-generator Molex Molex 0.30mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0140, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator JST PHD series connector, 53261-1771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator Connector Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776595 12A || order number: 1843855 8A 160V Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 10.
- Hole Total plated holes.
- Large "rules": { PCB initial layout, no.
- Vertex 6.46159 -1.49783 20 vertex 0.408138 6.48717 19.9.