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Vertex -5.078753e+000 9.622872e-001 2.484855e+001 facet normal 0.172963 0.0922671 0.980597 vertex -5.35022 5.0946 6.88312 facet normal 0.106347 0.024206 0.994034 facet normal -0.595624 0.758286 0.265017 facet normal -6.621969e-01 -7.493298e-01 -3.345441e-04 vertex -1.019954e+02 1.044215e+02 2.550000e+00 facet normal 0.63438 -0.767815 0.0895698 vertex 6.58293 0.759029 7.7465 vertex 4.98277 4.13938 7.73103 facet normal -0.0980238 -0.995184 -0 facet normal -4.720716e-001 8.093097e-001 3.495229e-001 facet normal -0.367708 -0.00385378 0.929933 vertex -7.37107 0.303284 6.90571 facet normal -0.629653 -0.76827 0.115322 facet normal -0.195087 0.980786 1.33453e-06 vertex 1.04125 -3.21788 6.59 facet normal -0.828666 -0.0817378 0.553744 facet normal -0.875976 0.471404 0.102197 vertex -4.71011 -0.41258 21.7538 facet normal 0.631369 0.769324 0.0975348 vertex 7.4445 -5.04732 4.51216 facet normal -0.946371 0.307492 0.099151 facet normal -1.011997e-14 5.429241e-15 -1.000000e+00 d8eca8dc7e Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 More repo cleanup, adopt github .gitignore file afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 62e17d71-a82e-47f7-8a14-a0885fbe0008) Final revision; added custom DRC as project file Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file ) ) Latest commits for file Panels/QuentinEF.ttf PSU/Synth Mages Power Word Stun Panel.kicad_pcb Synth Mages Power Word Stun.kicad_pcb alternate "" input line From 5505000471ab249f70d985a8f814bce077fb47b2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Optional capacitor socket # Temporary files fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* .

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