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-6.448911e-001 0.000000e+000 vertex -3.825564e+000 -4.191461e+000 1.747200e+001 facet normal -0.954697 -0.292532 0.0545798 vertex -5.60068 -4.19817 7.78686 facet normal 4.225726e-001 1.881635e-003 9.063271e-001 vertex -5.152617e+000 -1.091150e+000 2.491820e+001 facet normal -0.538413 0.714663 0.446506 facet normal -8.506957e-01 1.781115e-03 5.256555e-01 vertex -1.084234e+02 9.725134e+01 1.113305e+01 vertex -1.084033e+02 9.725134e+01 1.116563e+01 facet normal -4.803516e-01 -8.770760e-01 -3.417321e-04 vertex -1.006624e+02 1.053036e+02 2.550000e+00 facet normal -0.865129 -0.462436 0.19418 facet normal -0.957361 0.114987 0.265023 facet normal 4.720713e-001 -8.093082e-001 3.495267e-001 vertex -2.733856e+000 3.052276e+000 2.480400e+001 facet normal -0.233262 -0.84961 0.473025 vertex 5.03912 4.29172 7.34278 facet normal 0.88186 0.471361 -0.0119414 facet normal 0.875977 -0.471404 0.102188 facet normal 0.290283 0.956941 -5.32302e-07 facet normal -9.807886e-01 1.950737e-01 -2.437386e-04 vertex -1.043967e+02 1.005018e+02 3.455000e+01 facet normal -0.734373 -0.325742 0.595474 facet normal -0.980786 0.195087 0 facet normal 0.499974 0.86604 1.36818e-05 vertex -2.69039 -1.09142 18.554 facet normal 0.23112 0.46415 0.855072 facet normal -0.0820554 0.0808315 0.993344 vertex -5.39153 -4.12931 7.87036 facet normal 0.290515 0.956797 -0.0118781 facet normal -8.211016e-01 6.494083e-03 5.707451e-01 facet normal 0.0546159 -0.4548 0.888917 facet normal 0.0819688 -0.0815293 0.993295 vertex -5.39246 -4.12472 7.87006 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH] Final revision; added custom DRC as project file tstamp 6b7d6cc6-a11c-4566-a5f2-ddde4d827642) Final revision; added custom DRC as project file tstamp 885d8854-95c7-40d1-bee9-0e598504ab1c) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file tstamp eb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with exploratory 8hp layout.

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