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Alt tag, Alice Grove bigger img Subject: [PATCH] Notes from MK's PCB livestream # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0 Module Spellbook Pages Fab Plant.

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