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Back0.77296 -0.634342 -0.0119617 facet normal 0.875976 0.471404 0.102197 facet normal -1.284288e-001 -2.247502e-001 9.659158e-001 vertex 4.396920e+000 3.478450e+000 2.494118e+001 facet normal 8.477229e-01 3.604418e-03 5.304271e-01 facet normal 0.772567 -0.634832 0.0113625 facet normal -0.0729258 0.976256 0.203976 facet normal -8.979480e-01 -1.162584e-03 -4.401001e-01 facet normal 9.659144e-001 4.301482e-003 2.588261e-001 facet normal 0.452781 0.137351 0.880979 facet normal 7.871526e-01 0.000000e+00 6.167582e-01 facet normal -0.36633 -0.925211 0.0989244 facet normal -0.532833 -0.843291 -0.070358 facet normal 8.244231e-16 -2.375573e-15 -1.000000e+00 facet normal 0.472777 0.88054 0.0336276 facet normal -0.0819801 0.0822463 0.993235 vertex -7.37473 -0.0747576 6.86461 facet normal 2.507905e-001 4.366441e-001 8.639711e-001 vertex -3.484193e+000 -2.849256e+000 2.494118e+001 facet normal -9.572431e-01 -2.892846e-01 -1.847311e-05 facet normal -0.0221424 0.0970097 -0.995037 facet normal -0.989353 -0.0972815 0.108241 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository https://gitlab.com/rsholmes/precadsr Submodules From 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Mon Sep 17 00:00:00 2001 .../Panels/FIREBALL VCO.png | Bin 0 -> 406884 bytes ...uther_triangle_vco_quentin_v3_only_art.stl | Bin 0 -> 30552 bytes From bada0399ca1e4fb2dd01b4ec5312596f167b34e1 Mon Sep 17 00:00:00 2001 .../Panels/MAGIC MOUTH.png | Bin 0 -> 292681 bytes rename 3D Printing/{ => Cases}/6u_wing_v1.scad | 0 3D Printing/Rails/18hp_innie.stl Normal file Unescape Hardware/Panel/precadsr-panel/fp-lib-table Normal file Unescape Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod Normal file Unescape Schematics/Enlarge/Enlarge.kicad_sch Normal file View File # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Pcbnew) Initial version *.dsn *.ses Latest commits for file Fireball/Fireball_panel.kicad_dru RV4 FM LVL Binary files /dev/null and b/Panels/FIREBALL VCO.png differ Binary files a/Panels/futura light bt.ttf differ Latest commits for file Schematics/SynthMages.pretty/Switch.dcm From e97ef3972850f598b56fc0365b7ac9a8c525cde5 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Notes from MK's PCB livestream # Format documentation: https://kicad.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 14162964f93e8c9aadec1d2edfbf49ea0b8bcb52 Add MK manuals 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation e49f4ab127dc081ee1c77dd21e80d128628a1152 531ebcae92ad8ad00635060e3583259ee13cc12b 8-pin, one 14-pin and one with an.