3
1
Back

4975 lines Latest commits for branch panel_tweaking Add scad for v3.2 3afa35e4b1 PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces PCB initial layout, no traces Fireball/Fireball.kicad_prl | 4 .../PCB/precadsr_Gerbers/precadsr-PTH.drl | 207 .../PCB/precadsr_Gerbers/precadsr-job.gbrjob | 128 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-F_Paste.gbr | 15 .../precadsr-panel-PasteTop.gtp | 15 .../precadsr-panel-SilkBottom.gbo | 799 .../precadsr-panel-drl_map.pdf | Bin 12724 -> 0 bytes Binary files /dev/null and b/Images/IMG_6777.JPG differ Binary files /dev/null and b/Schematics/MK_Schematic.png differ Binary files /dev/null and b/3D Printing/Panels/image.png differ From ef3a1f8c03719dbc0f150781ee9810f0ed7b4301 Mon Sep 17 00:00:00 2001 Subject: [PATCH 1/2] Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement e8295830c4 STLs, 10hp version, others schematics thickness=2; label_inset_height = thickness-1; STLs, 10hp version, others schematics b404e3f9c5 Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file polygon (pts New KiCad version; non Al panel Gerbers # Netlist files (exported from Pcbnew) *.dsn.

New Pull Request