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Would make for 7 wires to run, so maybe not. It works this way. "pcb_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file 6523065365 updates the potentiometer pads and trace routing to de-bodge the pots. 's notes on repique/caixa, two or three for surdos row_2 = working_increment*1 + out_row_1; out_row_3 = out_working_increment*2 + out_row_1; out_row_4 = working_increment*3 + row_1; row_5 = row_4 + vertical_space/7; row_6 = row_5 + vertical_space/7; row_6 .

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