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Back[PATCH 09/13] Notes from MK's PCB livestream # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated.
- Clf_handle_diameter, 2, 2, 2, true.
- -9.017155e-001 -3.614251e-003 4.323149e-001 vertex 4.053363e+000 2.321364e+000 2.479508e+001 facet.
- -8.616847e-001 6.978928e-002 facet normal -0.360203 0.282966.
- U3 | 1 | SW_Push | Push.