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Hard_sync Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in to pause the sequence. Probably can't do, or impractical: - CV-controlled clock. Presumably the CV in that pauses the clock and keeps current gate open whenever the voltage.

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