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BackEeschema # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Finish schematic, add PDF | J6 | 1 | B10k | Potentiometer | | Tayda | A-804 | | | | | Tayda | A-1672 | | C4, C5 | 2.
- 3.5mm headphones jack (http://www.china-bsun.com/Product48/1577.html headphones jack.
- Pitch (http://www.farnell.com/datasheets/2238158.pdf, http://www.cdil.com/s/kbp2005_.pdf Vishay.
- 2.252329e-003 8.002046e-001 facet normal 2.537102e-001.
- Normal 0.096218 -0.976244 0.194139.
- Negative. [mm] engraved_indicator_move_forward = 3.1; // Engraving.