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THT HiLink board mount | | | | | | | | | | | | | | | Tayda | A-1605 | | | J9 | 3 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92"/> 2 pin Molex connector KK254 Molex header 2.54 mm spacing | | | | | | Tayda | A-553 | | | J10 | 1 | | | D3, D4, D5, D6, D7, D8, D9, D10 | 8 "use_height_for_length_calcs": true From 01bb4964a63ffeda0774c500204d2687e8f4164c Mon Sep 17 00:00:00 2001 Subject: [PATCH] PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups *-backups More repo cleanup, adopt github .gitignore file # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak Initial kicad, images, gitignore for kicad backups afea9d5a2c Final revision; added custom DRC as project file polygon (pts Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability f45c980890b44925f97883520535060dead99dd7 Collect other files not yet the desired effect because it is up to 1amp https://www.youtube.com/watch?v=pQKN30Mzi2g - maybe not as efficient as a full bridge rectifier; could use fewer caps that way PSU/psu.diy Executable file View File true L1 2.

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