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Filmoscope Quentin/Panels/POLYMORPH.png Normal file View File Thu 22 Apr 2021 10:45:56 AM EDT Mon 10 May 2021 12:33:34 AM EDT Generated from schematic into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF 2d3c489f2a More SR1 notation More SR1 notation main master PSU/Synth Mages Power Word Stun.kicad_pcb The Power Word Stun.kicad_prl Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl Normal file Unescape "Name": "Top Solder Paste" "Name": "Bottom Solder Paste" "Name": "Top Silk Screen" "Name": "Top Solder Paste" "Name": "Top Solder Paste" "Name": "Bottom Silk Screen" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Name": "Bottom Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file Unescape ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-B_SilkS.gbr Normal file Unescape HP = 5.08; // 5.08, must explicitly account for margin at edges width = 10; label_font = 6; //knob_radius saw_out = [h_margin + working_width/4, row_1, 0]; fm_pot = [input_column - h_margin/2, bottom_row, 0]; fm_in = [first_col, fourth_row.

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