3
1
Back

Hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Merge pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces }, More tweaks after pro review "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", More tweaks after pro review Fireball/Fireball.kicad_pro | 8 | 1N4148 .

New Pull Request