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Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 12821 bytes .../Panels/COLOR SPRAY.png | Bin 0 -> 461484 bytes Panels/title_test_36.stl | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 0 -> 11692 bytes .../Panels/HOLD PORTAL.png | Bin 16700 -> 0 bytes Latest commits for file Panels/luther_triangle_10hp_rib_space_fixes.stl main MK_VCO/Panels/Font files/futura medium bt.ttf and /dev/null differ Binary files /dev/null and b/Futura Heavy BT.ttf (grid_origin 84.5 17.5 Mark board for extraction A symbol representing annotation for tab placement (condition "A.Type == 'via' && B.Type == A.Type" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'via' && B.Type == A.Type && A.Net != B.Net" condition "A.Type == 'via'" condition "A.Type == 'pad' && B.Type == A.Type" condition "A.Type == 'pad' && B.Type .

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