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"similar_labels": "warning", More tweaks after pro review "different_unit_footprint": "error", "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those 7022ad9ddb couple more minor clearance tweaks couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices Add CV in implement a DC offset via non-inverting.

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