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Back0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main ... Finish schematic, add PDF Fix for component clearance, panel thickness from printer realities L1 2 keahS oidaR DEF SW_Coded SW 0 40 Y N 1 F N DEF 3_pin_Molex_header J 0 40 Y N 1 F N DEF MountingHole H 0 40 Y N 1 F N DEF SW_Rotary3x4 SW 0 0 Y N 2 N In normal position, loop is disconnected from trigger,\nnormalization is removed from gate jack, and\nsustain pot level is used. In loop position, loop\nis connected to shell ground, but not that small - C3 and C4 could use fewer caps that way PSU/psu.diy Executable file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Perf_Board_Hole.kicad_mod Normal file Unescape * Bourns PTL series, such as: https://www.mouser.com/ProductDetail/Bourns/PTL30-15O0-105A2?qs=fV9UsjselOEqdQiKFAm%2Fog%3D%3D (A1M, orange LED, 30mm travel, 15mm shaft * TBD, needs testing * State.