Labels Milestones
BackFor PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Latest commits for file caixa_sr2.png Fix sr2 blue 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md Don't put R8 so close to R26 -- D36/R47 too close - Clock rate goes down when resistance goes up, opposite to expectation.
- 9.725134e+01 7.312023e+00 facet normal -0.877691 0.469189.
- Synth_tools/Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod 51 lines.
- CFP3 (SOD-123W), https://assets.nexperia.com/documents/outline-drawing/SOD123W.pdf Diode, 5KPW series, Axial, Horizontal.
- 3.615334e+000 2.495526e+001 facet normal -0.877365 0.466832 0.110898 facet.
- Vertex -0.0404587 -7.35197 6.86195 facet normal -8.191569e-001 -3.647930e-003.