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All source code must retain the above copyright notice and this permission notice shall be included in repo Latest commits for file Images/PXL_20210831_000949090.jpg 2cb8e5eaf6 Go to file 74231bd333 Port in fixes from v1.1 SMT updates SMT updates SMT updates SMT updates Checkpoint after converting most things to SMD 53c46eece1 Still trying to implement chaining 1aa48a179a Add splits and labels to get 1:1 between schematic and PCB, no warnings d62e7c6861 More work finding space for everything, lining things up more Binary files a/Panels/futura medium bt.ttf Latest commits for branch bugfix/v1.1 Add position for resistor between coarse and +12V, value unknown c5e8dbdd1f Align panel to integer pseudo-origin, remove testing text, decrease title label font so we don't need a hole.

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