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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Latest commits for file Fireball/Fireball.kicad_prl couple more GND-stitch vias Latest commits for file Fireball/Fireball.kicad_dru | 102 Fireball/Fireball.kicad_pro | 4 | 1M | Resistor | | | J12 | 1 Hardware/lib/aoKicad | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x2 (see build notes) 1 SIP socket, 2.54 mm, 1x2 (see build notes) 1 SIP socket, 2.54 mm, 1x4 Pin header, 2.54 mm, 1x10 | | | | | J8 | 1 | AudioJack2_SwitchT | Audio Jack, 2 Poles (Mono / TS)
- -0.768445 0.630708 0.108161 facet normal 5.194410e-01 0.000000e+00.
- MS3? TBD. Note: Mid-surdos start with MS3.