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Slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request 'Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main afea9d5a2c Final revision; added custom DRC as project file ) ) New KiCad version; non Al panel Gerbers ) (filled_polygon New KiCad version; non Al panel Gerbers psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) New KiCad version; non Al panel Gerbers .gitignore | 2 | 10k | Resistor | | | | | Tayda | A-159 | | | | J7, J8, J9 | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x4 | | | | | U2 | 1 | 10R | Resistor | | | | S3 | 1 | 1 | 10nF | Ceramic capacitor | | | R16, R18, R26 | 3 | A1M | \*\*Potentiometer, 16 mm have been.

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