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BackPin (https://www.qorvo.com/products/d/da007268), generated with kicad-footprint-generator ipc_gullwing_generator.py SOP, 8 Pin (JEDEC MO-153 Var JC https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator ipc_gullwing_generator.py 44-Lead Plastic Quad Flat, No Lead Package (MR) - 9x9x0.9 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf eSOP-12B SMT Flat Package with Heatsink Tab, https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf Power Integrations variant of 10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 7 removed (Microchip Packaging Specification 00000049BS.pdf, http://www.onsemi.com/pub/Collateral/NCP1207B.PDF 8-Lead Plastic DFN (5mm x 3mm) (see Linear Technology DFN_6_05-08-1703.pdf 6-Lead Plastic Dual Flat No-Lead Package, Body 3.0x3.0x0.8mm, Texas Instruments EUS 5.
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