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Resistor | | R3, R21 | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through.

Vertex 4.096346e+000 -8.363258e-001 2.484855e+001 facet normal -0.630673.
Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill0.8mm.kicad_mod create mode 100644.

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