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{KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Minor layout tweaks merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main 1705ad98fb Put title box in PDF export' (#4) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main ... Add notes about wiring SW15 cross-board Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Add some.

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