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BackFrom Eeschema *.net # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes.
- -9.783644e-01 facet normal -0.875976 0.471404.
- 1.118030e+000 9.983999e+000 vertex -4.278750e+000.
- 4.8mm Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire.
- 2x33, 2.54mm pitch, 6mm.