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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Latest commits for file Schematics/Luthers_Perfboard.pdf From dd8c61c34faaeb27b8a193b7a0410df7bb5b6b87 Mon Sep 17 00:00:00 2001 Subject: [PATCH] rm project libraries Hardware/PCB/precadsr/fp-lib-table | 1 | SW_SPDT | SPDT miniature toggle switch | | | | C3, C4, C11 | 2 | 4.7k | Resistor | | | | Tayda | A-1672 | | | | | C3 | 1 | Conn_01x10 | Pin socket, 2.54 mm, 1x4 | | | C2 | 1 | SW_3PDT_x3 | Switch, triple pole double throw, separate symbols
- -7.693146e-01 -1.734006e-04 6.388701e-01 facet normal 2.964451e-001 9.550499e-001 0.000000e+000.
- 4.226319e-001 facet normal -1.418057e-13.