synth_mages/synth_tools
3
1
Fork 0

Labels Milestones

Back

F.Mask" "Notes": "Layer F.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF | J6 | 1 | 2_pin_Molex_connector | 2 Hardware/lib/Kosmo_panel | 2 | 1N5817 | Schottky Barrier Rectifier Diode, DO-41"/> 9.341726e+00 facet normal -8.416038e-01 3.471391e-03 -5.400843e-01 facet normal.

  • -3.036929e-01 0.000000e+00 facet normal 0.989357 0.0973162 0.108179.
  • From Eeschema) *.net # Autorouter files (exported from.
    • New Pull Request
    0 Open 0 Closed
    Label
    Use alt + click/enter to exclude labels
    All labels No label
    Milestone
    All milestones No milestones
    Project
    All projects No project
    0 Open 0 Closed
    Label
    Clear labels
    Milestone
    No milestone
    Projects
    Clear projects