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BackAnd R1, probably a result of KiCad adding junctions during a component move. This needs to be even. Odd values are -=1 difference() { union() { Panels/luther_triangle_10hp_pcb_holder.stl Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_26.stl Executable file View File Panels/FireballSpellSmall.png Executable file View File Panels/luther_triangle_vco_quentin_v2.scad Normal file View File Images/PXL_20210831_004139245.jpg Normal file Unescape ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated.
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