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Back# Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm.
- /* [Default values] */ // // Enable.
- 2.250131e-001 9.659145e-001 vertex -8.161444e-001 -5.644413e+000.
- 156.07 (end 175.136712 137.23.
- 1.060618e+01 facet normal 3.544368e-15 -5.053389e-15 1.000000e+00 facet.