synth_tools

Back

Entries. # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod Normal file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Dual_Mounting_Holes.kicad_mod Normal file View File 3D Printing/Panels/Radio_shaek_standoff_padded.stl Normal file View File 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png' 054c37512afd84e9f4dd43316902a76ae73fd917 Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png' abc39a50d6 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png From dcaec240831d28b722a7d7988287c76a1461e439 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/SPIDER CLIMB.png differ Latest commits for file Panels/label_test.stl From f5fc556ca298718ed9c38de316ac4c166fbbe181 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add polygon calculation for wing plates Add VCA shaek layout Add VCA shaek layout 4c5e03f875 re-re-remove the mysterious extra trace Add notes about UX component wiring D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock Out - 1K to TP5 Gate Out - 1K to U3-7 PSU/Synth Mages Power Word Stun Panel.kicad_prl | 77 Schematics/Enlarge/Enlarge.kicad_pro | 475 create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/CP_Radial_D5.0mm_P2.00mm.kicad_mod create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Jack_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-Edge_Cuts.gbr create mode 100644 Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_Mask.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/3PDT-toggle-switch-1M-seriesx.kicad_mod create mode 100644 .gitmodules delete mode 100644 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png differ Latest commits for file Datasheets/BC546A-MCC.pdf Fireball/fp-info-cache Normal file View File Panels/futura medium bt.ttf Normal file Unescape Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-B_Paste.gbr Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_SilkS.gbr Normal file View File Images/IMG_6770.JPG Normal file View File 3D Printing/Pot_Knobs/FS_PotiKnob_d6D14h9.stl Executable file View File.

New Pull Request

Labels Milestones