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0.0331891 0.780252 0.624584 facet normal 6.013306e-01 -7.990003e-01 -3.390242e-04 vertex -1.018688e+02 9.327779e+01 1.055000e+01 facet normal 9.975497e-001 4.442016e-003 6.982000e-002 vertex -4.008400e+000 7.700729e-001 2.470218e+001 facet normal 0.758298 -0.622316 0.194183 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt dd8c61c34f A couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices 4d8e233e93 Add CV (and knob) controlled glide to schematic Add pulldown resistors for reset debounce cap; formatting 2c2abd8837 checkpoint before getting really weird with WireIt dd8c61c34f A couple more.

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