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Back"Layer B.Cu" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 580484 bytes .../Panels/Radio_shaek_standoff_padded.stl | Bin 11692 .
- 1990834 (https://www.phoenixcontact.com/online/portal/gb/?uri=pxc-oc-itemdetail:pid=1990834), generated with kicad-footprint-generator ipc_noLead_generator.py.
- 29.20mm diameter 28mm Inductor.
- 4.15202 0.0392752 18.7299 facet normal 0.630715 -0.768435 0.108196.