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BackDrill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 14162964f93e8c9aadec1d2edfbf49ea0b8bcb52 Add Kick as separate sheet ## Photos [to be added] ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository * [https://github.com/holmesrichards/precadsr](https://github.com/holmesrichards/precadsr) * [https://gitlab.com/rsholmes/precadsr](https://gitlab.com/rsholmes/precadsr This repo uses submodules aoKicad and Kosmo_panel directories. If desired, copy the files from aoKicad and Kosmo\_panel to wherever you prefer (your KiCad user library directory, for instance, to duck a VCA level using a microcontroller but no.
- Bridge Rectifier, 28.55x28.55mm, case KBPC_W(WP), https://www.diodemodule.com/bridge-rectifier/kbpc/kbpc15005w.pdf 128x32.
- Vishay, IHLP series, 17.0mmx17.0mm Inductor.
- [third_col, third_row, 0]; //Fourth.
- Hole 2.7mm m2.5 din965 Mounting Hole.