Labels Milestones
BackIrd*sin(lf0), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 Merge pull request 'Put title box in PDF export Schematics/Fireball_VCO.pdf | Bin 0 -> 138868 bytes Docs/precadsr_bom.md | 72 Hardware/PCB/precadsr/potsetc.sch | 4 Fireball/Fireball.kicad_sch | 120 Fireball/fp-info-cache | 36 ...ns_3296W_Vertical_screw_centered.kicad_mod | 36 Schematics/Fireball.kicad_sch | 4790 Schematics/Fireball_VCO.pdf | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 0 -> 138868 bytes Docs/precadsr_bom.md | 72 Hardware/PCB/precadsr/potsetc.sch | 4 | 100 nF | Unpolarized capacitor | | Knobs | | | R15, R17, R19 | 2 | | S3 | 1 | TL074 | Quad operational amplifier, DIP-14"/>