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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count.
- Normal 6.203522e-20 -3.662970e-15 1.000000e+00 facet normal.
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11310848 bytes Synth_Manuals/Module Summaries.ods
8.86128 3.26879 facet normal 0.0112271 0.0915932.